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acpl-3130/j313, ACNW3130 very high cmr 2.5 amp output current igbt gate driver optocoupler data sheet lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product features ? high speed response. ? very high cmr. ? bootstrappable supply current. ? safety approval: ul recognized - 3750 v rms for 1 min. for acpl-3130/acpl-j313 - 5000 v rms for 1 min. for ACNW3130 csa approval iec/en/din en 60747-5-5 approved - v iorm = 630 v peak for acpl-3130 (option 060) - v iorm = 1230 v peak for acpl-j313 - v iorm = 1414 v peak for ACNW3130 specifcations ? 2.5 a maximum peak output current. ? 2.0 a minimum peak output current. ? 40 kv/s minimum common mode rejection (cmr) at v cm = 1500 v ? 0.5 v maximum low level output voltage (v ol ) eliminates need for negative gate drive ? i cc = 5 ma maximum supply current ? under voltage lock-out protection (uvlo) with hysteresis ? wide operating v cc range: 15 to 30 volts ? 500 ns maximum switching speeds ? industrial temperature range: -40c to 100c applications ? igbt/mosfet gate drive ? ac/brushless dc motor drives ? industrial inverters ? switching power supplies (sps) note: a 0.1 f bypass capacitor must be connected between pins v cc and v ee . caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-3130 contains a gaasp led while the acpl-j313 and the ancw3130 contain an algaas led. the led is optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by these optocouplers make them ideally suited for directly driving igbts with ratings up to 1200 v/100 a. for igbts with higher ratings, the acpl-3130 series can be used to drive a discrete power stage which drives the igbt gate. the ancw3130 has the highest insulation voltage of v iorm = 1414 v peak in the iec/en/din en 60747-5-5. the acpl-j313 has an insulation voltage of v iorm = 1230 v peak and the v iorm = 630 v peak is also available with the acpl- 3130 (option 060). functional diagram acpl-3130 and acpl-j313 ACNW3130 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc n/c v o v ee truth table led v cc C v ee positive going (i.e., turn-on) v cc C v ee negative going (i.e., turn-off) vo off 0 - 30 v 0 - 30 v low on 0 - 11 v 0 - 9.5 v low on 11 - 13.5 v 9.5 - 12 v transition on 13.5 - 30 v 12 - 30 v high
2 ordering information acpl-3130 and acpl-j313 are ul recognized with 3750 vrms for 1 minute per ul1577. ACNW3130 is ul recognized with 5000vrms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel iec/en/din en 60747-5-5 quantity rohs compliant acpl-3130 -000e 300mil dip-8 50 per tube -300e x x 50 per tube -500e x x x 1000 per reel -060e x 50 per tube -360e x x x 50 per tube -560e x x x x 1000 per reel acpl-j313 -000e 300mil dip-8 x 50 per tube -300e x x x 50 per tube -500e x x x x 1000 per reel ACNW3130 -000e 400mil dip-8 x 42 per tube -300e x x x 42 per tube -500e x x x x 750 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: acpl-3130-560e to order product of 300mil dip gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval in rohs compliant. example 2: acpl-3130-000e to order product of 300mil dip package in tube packaging and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
3 package outline drawings acpl-3130 outline drawing (standard dip package / 300mil dip) acpl-3130 gull wing surface mount option 300 outline drawing 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. dimensions in millimeters and (inches). * marking code letter for option numbers. "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.5 mm (20 mils) max. 5 6 7 8 4 3 2 1 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) lead free ul logo device part number special program code eee avago nnnn yyww a ? test rating code z p pin 1 dot lot id date code
4 acpl-j313 outline drawing (300mil dip) acpl-j313 gull wing surface mount option 300 outline drawing 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) 9.80 0.25 (0.386 0.010) 1.78 (0.070) max. 1.19 (0.047) max. dimensions in millimeters and (inches). option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 5 6 7 8 4 3 2 1 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.80 0.25 (0.386 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.5 mm (20 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) lead free ul logo device part number special program code e e e avago n n n n y y w w a ? test rating code z p pin 1 dot lot id date code
5 ACNW3130 outline drawing (8-pin wide body package / 400mil dip) ACNW3130 gull wing surface mount option 300 outline drawing 5 6 7 8 4 3 2 1 11.15 0.15 (0.442 0.006) 1.78 0.15 (0.070 0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 7 typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 0.15 (0.354 0.006) max. 10.16 (0.400) typ. 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154) 1.00 0.15 (0.039 0.006) 7 nom. 12.30 0.30 (0.484 0.012) 0.75 0.25 (0.030 0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 0.15 (0.442 0.006) 9.00 0.15 (0.354 0.006) 1.3 (0.051) 13.56 (0.534) 2.29 (0.09) land pattern recommendation 1.78 0.15 (0.070 0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max. n n n n n n n n y y w w ? lead free a device part number date code pin 1 dot e e e lot id test rating code z avago
6 recommended pb-free ir profle regulatory information the acpl-3130/j313 and ACNW3130 are approved by the following organizations: ul approval under ul 1577, component recognition program, file e55361. csa approval under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-5 (acpl-3130 option 060 only, acpl-j313 and ACNW3130) approval under: iec 60747-5-5 en 60747-5-5:2011 din en 60747-5-5 (vde 0884-5):2011-11 recommended solder refow temperature profle 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200 c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/?0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/?0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. no te: non-halide fl ux should be used . 217 c ramp -down 6 c/sec. ma x. ramp -up 3 c/sec. ma x. 150 - 200 c * 260 +0/-5 c t 25 c t o peak 60 t o 150 sec. 15 sec. time within 5 c of a c tu al peak tempera ture t p t s prehea t 60 t o 180 sec. t l t l t smax t smin 25 t p time tempera ture no tes: the time from 25 c t o peak tempera ture = 8 minutes ma x. t smax = 200 c, t smin = 150 c no te: non-halide fl ux should be used . * rec ommended peak tempera ture for widebody 400mils p a ck a ge is 245 c
7 table 1. iec/en/din en 60747-5-5 insulation characteristics* description symbol acpl-3130 option 060 acpl-j313 ACNW3130 unit installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage f 150 v rms for rated mains voltage f 300 v rms for rated mains voltage f 450 v rms for rated mains voltage f 600 v rms for rated mains voltage f 1000 v rms i C iv i C iv i C iii i C iv i C iv i C iii i C iii i C iv i C iv i C iv i C iv i C iii climatic classifcation 55/100/21 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 2 maximum working insulation voltage v iorm 630 1230 1414 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1181 1670 2652 v peak input to output test voltage, method a* v iorm x 1.6=v pr , type and sample test, t m =10 sec, partial discharge < 5 pc v pr 1008 1968 2262 v peak highest allowable overvoltage (transient overvoltage tini = 60 sec) v iotm 6000 8000 8000 v peak safety-limiting values C maximum values allowed in the event of a failure, also see figure 41 and 42. case temperature input current output power t s i s, input p s, output 175 230 600 175 400 600 150 400 700 c ma mw insulation resistance at t s , v io = 500 v r s >10 9 >10 9 >10 9 w * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/en/din en 60747-5-5) for a detailed description of method a and method b partial discharge test profles. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. surface mount classifcation is class a in accordance with cecc 00802. table 2. insulation and safety related specifcations parameter symbol acpl-3130 acpl-j313 ACNW3130 units conditions minimum external air gap (clearance) l(101) 7.1 7.4 9.6 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 7.4 8.0 10.0 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 0.5 1.0 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti > 175 > 175 > 200 v din iec 112/vde 0303 part 1 isolation group iiia iiia iiia material group (din vde 0110, 1/89, table 1) all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
8 table 3. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 c average input current i f(avg) 25 ma 1 peak transient input current (<1 s pulse width, 300pps) i f(tran) 1.0 a reverse input voltage acpl-3130 v r 5 v acpl-j313 5 v ACNW3130 5 v high peak output current i oh(peak) 2.5 a 2 low peak output current i ol(peak) 2.5 a 2 supply voltage v cc C v ee 0 35 v input current (rise/fall time) t r(in) /t f(in) 500 ns output voltage v o(peak) 0 v cc v output power dissipation p o 250 mw 3 total power dissipation p t 295 mw 4 lead solder temperature acpl-3130 260c for 10 sec., 1.6 mm below seating plane acpl-j313 ACNW3130 260c for 10 sec., up to seating plane solder refow temperature profle see package outline drawings section table 4. recommended operating conditions parameter symbol min. max. units note power supply v cc - v ee 15 30 v input current (on) acpl-3130 i f(on) 7 16 ma acpl-j313 ACNW3130 10 16 ma input voltage (off) v f(off) - 3.6 0.8 v operating temperature t a - 40 100 c
9 table 5. electrical specifcations (dc) over recommended operating conditions (t a = -40 to 100c, for acpl-3130,acpl-j313 i f(on) = 7 to 16ma, for ACNW3130 i f(on) = 10 to 16ma, v f(off) = -3.6 to 0.8 v, v cc = 15 to 30 v, v ee = ground) unless otherwise specifed. all typical values at t a = 25c and v cc - v ee = 30 v, unless otherwise noted. parameter symbol device min. typ. max. units test conditions fig. note high level output current i oh 0.5 1.5 a v o = v cc C 4 2, 3, 21 5 2.0 a v o = v cc C 15 2 low level output current i ol 0.5 2.0 a v o = v ee + 2.5 5, 6, 22 5 2.0 a v o = v ee + 15 2 high level output voltage v oh v cc -4 v cc -3 v i o = -100 ma 1, 3, 23 6, 7 low level output voltage v ol 0.1 0.5 v i o = 100 ma 4, 6, 24 high level supply current i cch 2.5 5.0 ma output open, i f = 7 to 16 ma 7, 8 low level supply current i ccl 2.5 5.0 ma output open, v f = -3.0 to +0.8 v threshold input current low to high i flh acpl-3130 2.3 5.0 ma i o = 0 ma, v o > 5 v 9, 17, 25 acpl-j313 1.0 5.0 ma i o = 0 ma, v o > 5 v 10, 18, 25 ACNW3130 2.3 8.0 ma i o = 0 ma, v o > 5 v 11, 17, 25 threshold input voltage high to low v fhl 0.8 v i o = 0 ma, v o > 5 v input forward voltage v f acpl-3130 1.2 1.5 1.8 v i f = 10 ma 19 acpl-j313 1.2 1.6 1.95 v i f = 10 ma 20 ACNW3130 1.2 1.6 1.95 v i f = 10 ma 20 temperature coefcient of input forward voltage d v f / d t a acpl-3130 -1.6 mv/c i f = 10 ma acpl-j313 -1.3 mv/c i f = 10 ma ACNW3130 -1.3 mv/c i f = 10 ma input reverse breakdown voltage bv r acpl-3130 5 v i r = 10 a acpl-j313 3 v i r = 100 a ACNW3130 3 v i r = 100 a input capacitance c in acpl-3130 60 pf f = 1 mhz, v f = 0 v acpl-j313 70 pf f = 1 mhz, v f = 0 v ACNW3130 70 pf f = 1 mhz, v f = 0 v uvlo threshold v uvlo+ 11.0 12.3 13.5 v i f = 10 ma, v o > 5 v 26, 38 v uvloC 9.5 10.7 12.0 v i f = 10 ma, v o > 5 v 26, 38 uvlo hysteresis uvlo hys 1.6 v i f = 10 ma, v o > 5 v 26, 38
10 table 6. switching specifcations (ac) over recommended operating conditions (t a = -40 to 100c, for acpl-3130,acpl-j313 i f(on) = 7 to 16ma, for ACNW3130 i f(on) = 10 to 16ma, v f(off) = -3.6 to 0.8 v, v cc = 15 to 30 v, v ee = ground) unless otherwise specifed. all typical values at t a = 25c and v cc - v ee = 30 v, unless otherwise noted. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 0.10 0.30 0.50 s rg = 10 w , cg = 10 nf, f = 10 khz, duty cycle = 50% 12,13, 14, 15, 16, 27 16 propagation delay time to low output level t phl 0.10 0.30 0.50 s pulse width distortion pwd 0.3 s 17 propagation delay diference between any two parts or channels pdd (t phl C t plh ) -0.35 0.35 s 39, 40 12 rise time t r 0.1 s 27 fall time t f 0.1 s uvlo turn on delay t uvlo on 0.8 s i f = 10 ma, v o > 5 v 26 uvlo turn of delay t uvlo off 0.6 s i f = 10 ma, v o > 5 v 26 output high level common mode transient immunity |cm h | 40 50 kv/ s t a = 25c, i f = 10 to 16 ma, v cm = 1500 v, v cc = 30 v 27 13, 14 output low level common mode transient immunity |cm l | 40 50 kv/ s t a = 25c, v f = 0 v, v cm = 1500 v v cc = 30 v 27 13, 15 table 7. package characteristics over recommended temperature (t a = -40 to 100c) unless otherwise specifed. all typicals at t a = 25c. parameter symbol device min. typ. max. units test conditions fig. note input-output momentary withstand voltage** v iso acpl-3130 3750 v rms rh < 50%, t = 1 min., t a = 25c 8, 11 acpl-j313 3750 v rms 9, 11 ACNW3130 5000 v rms 10, 11 resistance (input-output) r i-o acpl-3130 10 12 w v i-o = 500 v 11 acpl-j313 10 12 w v i-o = 500 v ACNW3130 10 12 10 13 w v i-o = 500 v, t a = 25c 10 11 w v i-o = 500 v, t a = 100c capacitance (input-output) c i-o acpl-3130 0.6 pf freq=1 mhz acpl-j313 0.8 pf freq=1 mhz ACNW3130 0.5 0.6 pf freq=1 mhz led-to-case thermal resistance q lc 467 c/w thermocouple located at center underside of package 32 led-to-detector thermal resistance q ld 442 c/w 32 detector-to-case thermal resistance q dc 126 c/w 32 ** the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specifcation or avago application note 1074 entitled optocoupler input-output endurance voltage.
11 figure 1. v oh vs. temperature. notes: 1. derate linearly above 70 c free-air temperature at a rate of 0.3 ma/c. 2. maximum pulse width = 10 s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0 a. see applications section for additional details on limiting i oh peak. 3. derate linearly above 70 c free-air temperature at a rate of 4.8 mw/c. 4. derate linearly above 70 c free-air temperature at a rate of 5.4 mw/c. the maximum led junction temperature should not exceed 125c. 5. maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. in this test v oh is measured with a dc load current. when driving capacitive loads v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o f 5 a). 9. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o f 5 a). 10. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 v rms for 1 second (leakage detection current limit, i i-o f 5 a). 11. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 12. the diference between t phl and t plh between any two acpl-3130, acpl-j313 or ACNW3130 parts under the same test condition. 13. pins 1 and 4 need to be connected to led common. 14. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15.0 v). 15. common mode transient immunity in a low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v). 16. this load condition approximates the gate load of a 1200 v/75a igbt. 17. pulse width distortion (pwd) is defned as |t phl - t plh | for any given device. figure 3. v oh vs. i oh . figure 2. i oh vs. temperature. figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol . (v oh - v cc ) - high output voltage drop - v -40 -4 t a - temperature - c 100 -1 -2 -20 0 0 2 0 4 0 -3 60 80 i f = 7 to 16 ma i out = -100 ma v cc = 15 to 30 v v ee = 0 v i oh - output high current - a -40 1.0 t a - temperature - c 100 1.8 1.6 -20 2.0 0 2 0 4 0 1.2 60 80 i f = 7 to 16 ma v out = (v cc - 4 v) v cc = 15 to 30 v v ee = 0 v 1.4 (v oh - v cc ) - output high voltage drop - v 0 -6 i oh - output high current - a 2.5 -2 -3 0.5 -1 1.0 1 . 5 -5 2.0 i f = 7 to 16 ma v cc = 15 to 30 v v ee = 0 v -4 100 c 25 c -40 c v ol - output low voltage - v -40 0 t a - temperature - c -20 0.25 0 2 0 0.05 100 0.15 0.20 0.10 40 60 80 v f (off) = -3.0 to 0.8 v i out = 100 ma v cc = 15 to 30 v v ee = 0 v i ol - output low current - a -40 0 t a - temperature - c -20 4 0 2 0 1 100 2 3 40 60 80 v f (off) = -3.0 to 0.8 v v out = 2.5 v v cc = 15 to 30 v v ee = 0 v v ol - output low voltage - v 0 0 i ol - output low current - a 2.5 3 0.5 4 1.0 1 .5 1 2.0 v f(off) = -3.0 to 0.8 v v cc = 15 to 30 v v ee = 0 v 2 100 c 25 c -40 c
12 figure 11. i flh vs. temperature. (ACNW3130) figure 12. propagation delay vs. v cc . figure 13. propagation delay vs. i f . figure 14. propagation delay vs. temperature. figure 15. propagation delay vs. rg. figure 8. i cc vs. v cc . figure 7. i cc vs. temperature. figure 9. i flh vs. temperature. (acpl-3130) figure 10. i flh vs. temperature. (acpl-j313) i cc - supply current - ma -40 1.5 t a - temperature - c 100 3.0 2.5 -20 3.5 0 2 0 4 0 2.0 60 80 v cc = 30 v v ee = 0 v i f = 10 ma for i cch i f = 0 ma for i ccl i cch i ccl i cc - supply current - ma 15 1.5 v cc - supply voltage - v 30 3.0 2.5 3.5 20 2.0 25 i f = 10 ma for i cch i f = 0 ma for i ccl t a = 25 c v ee = 0 v i cch i ccl i flh - low to high current threshold - ma -40 0 t a - temperature - c 100 3 2 -20 4 0 2 0 4 0 1 60 80 5 v cc = 15 to 30 v v ee = 0 v output = open i flh - low to high current threshold - ma -40 0 t a - temperature - c -20 5 0 2 0 1 100 2 3 40 60 80 v cc = 15 to 30 v v ee = 0 v output = open 4 i flh - low to high current threshold - ma -40 0 t a - temperature - c -20 5 0 2 0 1 100 2 3 40 60 80 v cc = 15 to 30 v v ee = 0 v output = open 4 t p - propagation delay - ns 15 100 v cc - supply voltage - v 30 400 300 500 20 200 25 i f = 10 ma t a = 25 c rg = 10 cg = 10 nf duty cycle = 50% f = 10 khz t plh t phl t p - propagation delay - ns 6 100 i f - forward led current - ma 16 400 300 500 10 200 12 v cc = 30 v, v ee = 0 v rg = 10 , cg = 10 nf t a = 25 c duty cycle = 50% f = 10 khz t plh t phl 14 8 t p - propagation delay - ns -40 100 t a - temperature - c 100 400 300 -20 500 0 2 0 4 0 200 60 80 t plh t phl i f = 10 ma v cc = 30 v, v ee = 0 v rg = 10 , cg = 10 nf duty cycle = 50% f = 10 khz t p - propagation delay - ns 0 100 rg - series load resistance - 50 400 300 10 500 30 200 40 t plh t phl v cc = 30 v, v ee = 0 v t a = 25 c i f = 10 ma cg = 10 nf duty cycle = 50% f = 10 khz 20
13 figure 17. transfer characteristics (acpl-3130 / ACNW3130) figure 18. transfer characteristics (acpl-j313) figure 19. i f vs. v f . (acpl-3130) figure 20. i f vs. v f . (acpl-j313 / ACNW3130) figure 21. i oh test circuit. figure 22. i ol test circuit. figure 16. propagation delay vs. cg. t p - propagation delay - ns 0 100 cg - load capaci tance - nf 100 400 300 20 500 40 200 60 80 t plh t phl v cc = 30 v, v ee = 0 v t a = 25 c i f = 10 ma rg = 10 duty cycle = 50% f = 10 khz v o - output voltage - v 0 0 i f - forward led current - ma 5 25 15 1 30 2 5 3 4 20 10 v o - output voltage - v 0 0 i f - forward led current - ma 1 35 2 5 5 15 25 3 4 10 20 30 i f - forward current - ma 1.10 0.001 v f - forward voltage - volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25 c i f v f + - 0.01 100 v f - forward voltage - volts 1.2 1.3 1.4 1.5 i f - forward current - ma 1.7 1.6 1.0 i f + t a = 25 c - v f 0.1 0.01 0.001 10 100 1000 0.1 f v cc = 15 to 30 v 1 3 i f = 7 to 16 ma + ? 2 4 8 6 7 5 + ? 4 v i oh 0.1 f v cc = 15 to 30 v 1 3 + - 2 4 8 6 7 5 2.5 v i ol + -
14 figure 23. v oh test circuit. figure 24. v ol test circuit. figure 25. i flh test circuit. figure 26. uvlo test circuit. figure 27. t plh , t phl , t r , and t f test circuit and waveforms. figure 28. cmr test circuit and waveforms. 0.1 f v cc = 15 to 30 v 1 3 i f = 7 to 16 ma + e 2 4 8 6 7 5 100 ma v oh 0.1 f v cc = 15 to 30 v 1 3 + - 2 4 8 6 7 5 100 ma v ol 0.1 f v cc = 15 to 30 v 1 3 i f + - 2 4 8 6 7 5 v o > 5 v 0.1 f v cc 1 3 i f = 10 ma + - 2 4 8 6 7 5 v o > 5 v 0.1 f v cc = 15 to 30 v 10 1 3 i f = 7 to 16 ma v o + - + - 2 4 8 6 7 5 10 khz 50% duty cycle 500 10 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 f v cc = 30 v 1 3 i f v o + - + - 2 4 8 6 7 5 a + - b v cm = 1500 v 5 v v cm ? t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh t v cm ? v ? t =
15 applications information eliminating negative igbt gate drive (discussion ap - plies to acpl-3130, acpl-j313, and ACNW3130) to keep the igbt frmly of, the acpl-3130 has a very low maximum vol specifcation of 0.5 v. the acpl-3130 realizes this very low v ol by using a dmos transistor with 1 w (typical) on resistance in its pull down circuit. when the acpl-3130 is in the low state, the igbt gate is shorted to the emitter by r g + 1 w . minimizing r g and the lead inductance from the acpl-3130 to the igbt gate and emitter (possibly by mounting the acpl-3130 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 29. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the acpl-3130 input as this can result in unwanted coupling of transient signals into the acpl- 3130 and degrade performance. (if the igbt drain must be routed near the acpl-3130 input, then the led should be reverse-biased when in the of state, to prevent the transient signals coupled from the igbt drain from turning on the acpl-3130.) figure 29. recommended led drive and application circuit. selecting the gate resistor (r g ) to minimize igbt switching losses. (discussion applies to acpl-3130, acpl-j313 and ACNW3130) step 1: calculate rg minimum from the i ol peak specifcation. the igbt and r g in figure 30 can be analyzed as a simple rc circuit with a voltage supplied by the acpl-3130. the v ol value of 2 v in the previous equation is a conservative value of v ol at the peak current of 2.5a (see figure 6). at lower r g values the voltage supplied by the acpl-3130 is not an ideal voltage step. this results in lower peak currents (more margin) than predicted by this analysis. when negative gate drive is not used v ee in the previous equation is equal to zero volts. figure 30. acpl-3130 typical application circuit with negative igbt gate drive. = = ? + = ? ? 3 8 7.2 2.5 2 5 15 i v v v r olpeak ol ee cc g + hvdc 3-phase ac - hvdc 0.1 f v cc = 18 v 1 3 + - 2 4 8 6 7 5 270 +5 v control input rg q1 q2 74xxx open collector + hvdc 3-phase ac - hvdc 0.1 f v cc = 15 v 1 3 + - 2 4 8 6 7 5 rg q1 q2 v ee = -5 v - + 270 +5 v control input 74xxx open collector
16 step 2: check the acpl-3130 power dissipation and increase r g if necessary. the acpl-3130 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output for the circuit in figure 30 with i f (worst case) = 16 ma, r g = 8 w , max duty cycle = 80%, q g = 500 nc, f = 20 khz and t a max = 85?c: power (p o ): pe parameter description i f led current v f led on voltage duty cycle maximum led duty cycle po parameter description i cc supply current v cc positive supply voltage v ee negative supply voltage e sw(rg,qg) energy dissipated in the acpl-3130 for each igbt switching cycle (see figure 31) f switching frequency figure 31. energy dissipated in the acpl-3130 for each igbt switching cycle. the value of 4.25 ma for i cc in the previous equation was obtained by derating the i cc max of 5 ma (which occurs at -40c) to i cc max at 85?c (see figure 7). since p o for this case is greater than p o(max) , r g must be increased to reduce the acpl-3130 power dissipation. for q g = 500 nc, from figure 31, a value of e sw = 4.65 j gives a r g = 10.3 . esw - energy per switching cycle - j 0 0 rg - gate resistance - 50 6 10 14 20 4 30 40 12 qg = 100 nc qg = 500 nc qg = 1000 nc 10 8 2 v cc = 19 v v ee = -9 v () f q ; r e v i p p p dutycycle v i p p p p g g sw cc cc g) o(switchin o(bias) o f f e o e t + = + = = + = ? ? ? ? ( ) ( c mw/ 8 . 4 c 15 - 250mw c @85 p mw 178 mw 189 mw 104 mw 85 20khz j 2 . 5 v 20 4.25ma p 23mw 0.8 1.8v 16ma p max o o e ? = > = + = ? + ? = = ? ? = ? ? ? ? ) ? () ( ) ( ) 93mw 85mw 178mw p - p p bias o max o max switching o = = = () () j 65 . 4 20khz 93mw p e max switching o max sw = = = f -
17 thermal model (discussion applies to acpl-3130, acpl-j313 and figure 32. thermal model. the steady state thermal model for the acpl-3130 is shown in figure 32. the thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. as shown by the model, all heat generated fows through q ca which raises the case temperature t c accordingly. the value of q ca depends on the conditions of the board design and is, therefore, determined by the designer. the value of q ca = 83c/w was obtained from thermal measurements using a 2.5 x 2.5 inch pc board, with small traces (no ground plane), a single acpl-3130 soldered into the center of the board and still air. the absolute maximum power dissipation derating specifcations assume a q ca value of 83c/w. from the thermal mode in figure 32 the led and detector ic junction temperatures can be expressed as: ACNW3130) t je = led junction temperature t jd = detector ic junction temperature t c = case temperature measured at the center of the package bottom q lc = led-to-case thermal resistance q ld = led-to-detector thermal resistance q dc = detector-to-case thermal resistance q ca = case-to-ambient thermal resistance * q ca will depend on the board design and the placement of the part. inserting the values for q lc and q dc shown in figure 32 gives: for example, given p e = 45 mw, p o = 250 mw, t a = 70c and q ca = 83c/w: t je and t jd should be limited to 125c based on the board layout and part placement ( q ca ) specifc to the application ? ld = 442 c/w t je t jd lc = 467 c/w dc = 126 c/w ca = 83 c/w* t c t a c 120 c 70 c/w 140 250 c/w 339 45mw t c/w 140 p c/w 339 p t a d e je = + + = + + = mw c 70 c/w 194 250 c/w 140 45 t c/w 194 p c/w 140 p t a d e jd + + = + + = mw mw ? ? ? ? ? ? ? ? ( ) ( ) () () a ca ld dc lc dc lc d ca dc ld lc e je t p || p t + + + + + + + = () ( a ca lc ld dc d ca ld dc lc dc lc e jd t || p p t + + + + + + + = ) ? ? ? ? ? ? () ( ) a ca d ca e je t c/w 57 p c/w 256 p t + + + + = () ( ) a ca d ca e jd t c/w 111 p c/w 57 p t + + + + = ? ? ? ?
18 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the directio n of current flow duri ng - dv cm /dt. +5 v + - v cc = 18 v 0.1 f + - - 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn figure 36. not recommended open collector drive circuit. the open collector drive circuit, shown in figure 36, cannot keep the led of during a +dv cm /dt transient, since all the current fowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr l performance. figure 37 is an alternative drive circuit which, like the recommended application circuit (figure 29), does achieve ultra high cmr performance by shunting the led in the of state. figure 35. equivalent circuit for figure 29 during common mode transient. cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 10 ma provides adequate margin over the maximum i flh of 5 ma to achieve 40 kv/s cmr. cmr with the led of (cmr l ) a high cmr led drive circuit must keep the led of (v f f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 35, the current fowing through c ledp also fows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) , the led will remain of and no common mode failure will occur. figure 34. optocoupler input to output capacitance model for shielded optocouplers. figure 33. optocoupler input to output capacitance model for unshielded optocouplers. led drive circuit considerations for ultra high cmr per - formance. (discussion applies to acpl-3130, acpl-j313, and ACNW3130) without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 33. the acpl-3130 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and optocoupler pins 5-8 as shown in figure 34. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or of ) during common mode transients. for example, the recommended application circuit (figure 29), can achieve 40 kv/s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections.
19 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v v o - output voltage - v 0 0 (v cc - v ee ) - supply voltage - v 10 5 14 10 15 2 20 6 8 4 12 (12.3, 10.8) (10.7, 9.2) (10.7, 0.1) (12.3, 0.1) t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference note: for pdd calcu lations the propagation delays are taken at the sa me temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on figure 39. minimum led skew for zero dead time. figure 38. under voltage lock out. under voltage lockout feature. (discussion applies to acpl-3130, acpl-j313, and ACNW3130) the acpl-3130 contains an under voltage lockout (uvlo) feature that is designed to protect the igbt under fault conditions which cause the acpl-3130 supply voltage (equivalent to the fully-charged igbt gate voltage) to drop below a level necessary to keep the igbt in a low resistance state. when the acpl-3130 output is in the high state and the supply voltage drops below the acpl-3130 v uvlo C threshold (9.5 < v uvlo C < 12.0) the optocoupler output will go into the low state with a typical delay, uvlo turn of delay, of 0.6 s. when the acpl-3130 output is in the low state and the supply voltage rises above the acpl-3130 v uvlo + threshold (11.0 < v uvlo + < 13.5) the optocoupler output will go into the high state (assumes led is on) with a typical delay, uvlo turn on delay of 0.8 s. dead time and propagation delay specifcations. (discussion applies to acpl-3130, acpl-j313, and ACNW3130) the acpl-3130 includes a propagation delay diference (pdd) specifcation intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 29) are of. any overlap in q1 and q2 conduction will result in large currents fowing through the power devices between the high and low voltage motor rails. figure 37. recommended led drive circuit for ultra-high cmr. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn of of led1) so that under worst-case conditions, transistor q1 has just turned of when transistor q2 turns on, as shown in figure 35. the amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay diference specifcation, pdd max , which is specifed to be 350 ns over the operating temperature range of -40c to 100c. delaying the led signal by the maximum propagation delay diference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the diference between the maximum and minimum propagation delay diference specifcations as shown in figure 40. the maximum dead time for the acpl-3130 is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of - 40c to 100c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
figure 41. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-5 for acpl-3130 (option 060) and acpl-j313. figure 42. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-5 for ACNW3130. figure 40. waveforms for dead time. t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) - (t phl min - t plh max ) = pdd* max - pdd* min *pdd = propagation delay difference note: for dead time and p dd calculations all propagation delays are taken at the s a me temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl min t phl max t plh max pdd* max (t phl- t plh ) max output power - p s , input current - i s 0 0 t s - case tem perature - c 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma) for acpl-3130 option 060 i s (ma) for acpl-j313 output power - p s , input current - i s 0 0 t s - case temperature - c 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 p s (mw) i s (ma) for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. obsoletes av01-0630en av02-0156en - october 14, 2013

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